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Altera High-Definition MultimediaInterface IP Core User GuideSubscribeSend FeedbackUG-HDMI2015.05.04101 Innovation DriveSan Jose, CA 95134www.altera.c

OpenCore Plus IP EvaluationAltera's free OpenCore® Plus feature allows you to evaluate licensed MegaCore® IP cores in simulationand hardware befo

HDMI Source42015.05.04UG-HDMISubscribeSend FeedbackSource Functional DescriptionThe HDMI source core provides direct connection to the Transceiver Nat

The source core accepts video, audio, and auxiliary channel data streams. The core produces a TMDS/TERC4 encoded data stream that would typically conn

Figure 4-3: Source Pixel Data Input Format RGB/YCbCr 4:4:4The figure below shows the RGB color space pixel bit-field mappings.47 32 31 16 15 0vid_data

The output from the WOP generator is an aux_de signal propagated backwards through the auxiliarysignal path to provide backpressure.Based on the HDMI

The encoder assumes the data valid input will remain asserted for the duration of a packet to complete. Apacket is always 24 clocks (in 1-symbol mode)

The core sends the auxiliary control packets on the active edge of the V-SYNC signal to ensure that thepackets are sent once per field.Source General

Bit-field Name Comment11:10 B Bar info data valid12 A0 Active information present14:13 Y RGB or YCbCr indicator15 Reserved Returns 019:16 R Active for

Table 4-3: HDMI Vendor Specific InfoFrame Bit-FieldsThe table below lists the bit-fields for VSI.The signal bundle is clocked by ls_clk.Bit-field Name

Bit-field Name Comment15:12 CT Audio format type17:16 SS Bits per audio sample20:18 SF Sampling frequency23:21 Reserved Returns 031:24 CXT Audio forma

ContentsHDMI Quick Reference...1-1HDMI Overview...

Figure 4-8: Source Audio EncoderTimestampSchedulerAuxiliary PacketGeneratorAuxiliary PacketGeneratorAuxiliary PacketGeneratorCTS, NOverride AIAudio In

Parameter Value DescriptionSupport auxiliary0 = No AUX1 = AUXDetermines if auxiliary channel encoding isincluded.Support deep color0 = No deep color1

Interface Port Type ClockDomainPort Direction DescriptionClockClock N/A ls_clk Input Link speed clockinput.8/8 (1x), 10/8(1.25x), 12/8 (1.5x),or 16/8

Interface Port Type ClockDomainPort Direction DescriptionVideo Data PortConduit vid_clk vid_data[N*48-1:0] Input Video 48-bit pixeldata input port.• I

Interface Port Type ClockDomainPort Direction DescriptionAuxiliary Data PortConduit ls_clk aux_ready Output Auxiliary datachannel validoutput.Conduit

Interface Port Type ClockDomainPort Direction DescriptionAudio PortConduit audio_clk audio_CTS[21:0] Input Audio CTS valueinput.Conduit audio_clk audi

Figure 4-9: Source Clock TreeThe figure shows how the different clocks connect in the source core.ResamplerFIFOSyncTMDS(TERC4)EncoderSyncSyncSyncHSSI[

HDMI Sink52015.05.04UG-HDMISubscribeSend FeedbackSink Functional DescriptionThe HDMI sink core provides direct connection to the Transceiver Native PH

Sink Channel Word Alignment and DeskewThe input stage of the sink is responsible for synchronizing the incoming parallel data channels correctly.The s

Figure 5-2: Channel Deskew DCFIFO ArrangementThe figure below shows the signal flow diagram of the deskew logic.AlignmentDetectionDCFIFOChannel 0rdreq

HDMI Hardware Demonstration Requirements...6-2Transceiver and Clockin

Sink Video ResamplerThe video resampler consists of a gearbox and a dual-clock FIFO (DCFIFO).The gearbox converts 8 bit-per-second (bps) data to 8-, 1

Figure 5-4: Auxiliary Data Stream SignalThe figure below shows the relationship between the data bit-field and its clock cycle based on 1-, 2-, or 4-s

Sink General Control PacketTable 5-1: General Control Packet Input FieldsBit Field Name Commentgcp[3:0]Color Depth(CD)CD3 CD2 CD1 CD0 Color depth0 0 0

Bit-field Name Comment19:16 R Active format aspect ratio21:20 M Picture aspect ratio23:22 C Colorimetry (for example: ITU BT.601, BT.709)25:24 SC Non-

Bit-field Name Comment60:58 3D_Ext_Data 3D extended dataSink Auxiliary Data PortThe auxiliary port is attached to external memory. This port allows yo

Audio Sample11 BCH3 PB27 BCH2 PB20 BCH1 PB13 BCH0 PB6 HBCH0General Control12 PB22 PB21 PB15 PB14 PB8 PB7 PB1 PB0 HB013 PB24 PB23 PB17 PB16 PB10 PB9 PB

High Bitrate (HBR) Audio Stream Packet36 PB22 PB21 PB15 PB14 PB8 PB7 PB1 PB0 HB037 PB24 PB23 PB17 PB16 PB10 PB9 PB3 PB2 HB138 PB26 PB25 PB19 PB18 PB12

MPEG Source InfoFrame61 PB24 PB23 PB17 PB16 PB10 PB9 PB3 PB2 HB162 PB26 PB25 PB19 PB18 PB12 PB11 PB5 PB4 HB263 BCH3 PB27 BCH2 PB20 BCH1 PB13 BCH0 PB6

Parameter Value DescriptionDirectionTransmitter = SourceReceiver = SinkSelect HDMI sink.Symbols per clock 1, 2, or 4 symbols perclockDetermines how ma

Table 5-6: Sink InterfacesN is the number of symbols per clock.Interface Port Type ClockDomainPort Direction DescriptionReset Reset N/A reset Input Ma

HDMI Quick Reference12015.05.04UG-HDMISubscribeSend FeedbackThe Altera High-Definition Multimedia Interface (HDMI) IP core provides support for next-g

Interface Port Type ClockDomainPort Direction DescriptionVideo Data PortConduit vid_clk vid_data[N*48-1:0] Output Video 48-bit pixeldata output port.I

Interface Port Type ClockDomainPort Direction DescriptionTMDS Data PortConduit ls_clk[0] in_b[N*10-1:0] Input TMDS encodedblue channel input.Conduit l

Interface Port Type ClockDomainPort Direction DescriptionAudio PortConduit ls_clk[0] audio_CTS[21:0] Output Audio CTS valueoutput.Conduit ls_clk[0] au

Interface Port Type ClockDomainPort Direction DescriptionAuxiliary Control PortConduit ls_clk[0] gcp[5:0] Output General ControlPacket output.Conduit

• 8-bpp—link speed clock divided by 1• 10-bpp—link speed clock divided by 1.25• 12-bpp—link speed clock divided by 1.5• 16-bpp—link speed clock divide

HDMI Hardware Demonstration62015.05.04UG-HDMISubscribeSend FeedbackThe Altera High-Definition Multimedia Interface (HDMI) hardware demonstration allow

Figure 6-1: HDMI Hardware Demonstration Block DiagramThe figure below shows a high level block diagram of the demonstration.Reconfiguration Management

Figure 6-2: Interface Signal Connections (Bitec HDMI 1.4b HSMC)UG-HDMI2015.05.04HDMI Hardware Demonstration Requirements6-3HDMI Hardware Demonstration

Figure 6-3: Adaptive Cable Equalizer and Level Shifter (Bitec HDMI 1.4b HSMC)6-4HDMI Hardware Demonstration RequirementsUG-HDMI2015.05.04Altera Corpor

Figure 6-4: Interface Signal Connections (Bitec HDMI 2.0 HSMC)UG-HDMI2015.05.04HDMI Hardware Demonstration Requirements6-5HDMI Hardware DemonstrationA

HDMI Overview22015.05.04UG-HDMISubscribeSend FeedbackThe Altera High-Definition Multimedia Interface (HDMI) IP core provides support for next generati

Figure 6-5: Adaptive Cable Equalizer and Level Shifter (Bitec HDMI 2.0 HSMC)Related Information• Arria V GX Starter Kit User Guide• Stratix V GX FPGA

Table 6-1: Tranceiver Configuration SettingsParametersSettingsReceiver TransmitterDatapath OptionsEnable TX datapath Off OnEnable RX datapath On OffEn

TX PMANumber of TX PLLs — 1Main TX PLL logical index — 0PPM detector threshold — 1000 PPMNumber of TX PLLreference clocks— 1TX PLL 0PLL type — CMURefe

Signal Direction ConnectionReceiver Interfacesrx_serial_data InputConnect to the HDMI TMDS data channel.• Bit 0: Blue channel• Bit 1: Green channel• B

Transmitter Interfacestx_std_coreclkin Input Connect to the clock that previously clocks the TX PCS andcore logic. This port is normally connected to

Figure 6-6: Software Process for PLL, Transmitter, or TX PLL ReconfigurationThe figure below shows the software process flow.Note: The Clocked Video I

Demonstration WalkthroughSetting up and running the HDMI hardware demonstration consists of four stages.You can use the Altera-provided scripts to aut

This script executes the following commands:• Generate IP catalog files• Generate the Qsys system• Create a Quartus II project• Create a software work

HDMI Simulation Example72015.05.04UG-HDMISubscribeSend FeedbackThe Altera HDMI simulation example evaluates the functionality of the HDMI IP core and

The testbench implements CRC checking on the input and output video. The testbench checks the CRCvalue of the transmitted data against the CRC calcula

Figure 2-1: Altera HDMI Block DiagramThe figure below illustrates the blocks in the Altera HDMI IP core.HDMITransmitterHDMIReceiverTDMS Channel 0HDMI

CommandGenerate the simulation files for theHDMI cores.• ip-generate --project-directory=./ --component-file=./hdmi_rx_single.qsys --output-directory=

CommandCompile and simulate the design in theModelSim software.Example successful result:# Resolution = # Resolution = 127 RX CRC = ee33 TX CRC =

Additional Information for High-DefinitionMultimedia Interface User GuideA2015.05.04UG-HDMISubscribeSend FeedbackDocument Revision History for HDMI Us

Figure 2-2: HDMI Video Stream DataActive VideoData IslandPreambleActiveAux/AudioVideoPreambleActive VideoVideoGuardBandVideoGuardBandData IslandGuardB

Each data stream section is preceded with guard bands and pre-ambles. These allow for accurate synchro‐nization with received data streams.Resource Ut

HDMI Getting Started32015.05.04UG-HDMISubscribeSend FeedbackThis chapter provides a general overview of the Altera IP core design flow to help you qui