
The source core accepts video, audio, and auxiliary channel data streams. The core produces a TMDS/
TERC4 encoded data stream that would typically connect to the high-speed transceiver parallel data
inputs.
Central to the core is the TMDS/TERC4 encoder. The encoder processes either video or auxiliary data.
Source TMDS/TERC4 Encoder
The source TMDS/TERC4 encoder implements 8-bit to 10-bit and 4-bit to 10-bit algorithms as defined in
the HDMI Specification Ver.2.0. Each channel has its own encoder.
The encoder processes symbol data at 1, 2, or 4 symbols per clock.
When the encoder operates in 2 or 4 symbols per clock, it also produces the output in the form of two or
four encoded symbols per clock.
The TMDS/TERC4 encoder also produces digital visual interface (DVI) signaling when you deassert the
mode input signal. DVI signaling is identical to HDMI signaling, except for the absence of data and video
islands and TERC4 auxiliary data.
Source Video Resampler
The core resamples the video data based on the current color depth.
The video resampler consists of a gearbox and a dual-clock FIFO (DCFIFO).
Figure 4-2: Source Video Resampler Signal Flow Diagram
The figure below shows the components of the video resampler and the signal flow between these
components.
Pixel Data [bpp:0]
1
vid_clk
DCFIFO
ls_clk
data
wr
wrclk
q
rd
rdclk
de
H-SYNC
V-SYNC
Phase
Counter
Gearbox Pixel Data [7:0]
H-SYNC
V-SYNC
de
Resampled
pp
bpp
The resampler adheres to the recommended phase encoding method described in HDMI Specification
Ver.1.4b.
• The phase counter must register the last packing-phase (pp) of the last pixel of the last active line.
• The resampler then transmits the pp value to the attached sink device in the General Control Packet
(GCP) for packing synchronization.
4-2
Source TMDS/TERC4 Encoder
UG-HDMI
2015.05.04
Altera Corporation
HDMI Source
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