APRO RUFD GDK-2010 HERMES Series © 2010 APRO Co., Ltd.
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1.1. Scope
This document describes the features and specifications of Industrial Rugged Metal GDK-2010 high capacity & high
performance USB Flash Disk – HERMES Series.
1.2. System Features
Rugged metal USB casing design to endure various rough environments
Compliant with USB specification 2.0 and downwards compatible to USB 1.0
SLC supports standard grade operating temperature 0°C to 70°C & industrial grade operating temperature -40° C ~
85° C
Complies with Microsoft Vista Ready-Boost® requirement.
Supports Ready Boost for Microsoft Vista O.S.
SLC USB Flash Disk capacities from 16GB to 64GB and MLC USB Flash Disk from 32GB to 128GB
Fixed disk type and optional for removable disk type
Performance up 30MB/sec
1.3. Technology Independence - Static Wear Leveling
In order to gain the best management for flash memory, Industrial Rugged Metal GDK-2010 high capacity & high
performance USB Flash Disk – HERMES Series supports Static Wear Leveling technology to manage the Flash system.
The life of flash memory is limited; the management is to increase the life of the flash product.
A static wear-leveling algorithm evenly distributes data over an entire Flash cell array and searches for the least used
physical blocks. The identified low cycled sectors are used to write the data to those locations. If blocks are empty, the
write occurs normally. If blocks contain static data, it moves that data to a more heavily used location before it moves the
newly written data. The static wear leveling maximizes effective endurance Flash array compared to no wear leveling or
dynamic wear leveling.
1.4. ECC Technology
Please refer to Figure--2. Figure--2 is a diagram illustrating an allocation method of a spare area in each page of a NAND
flash memory, wherein the specific ECC algorithm utilizes a Bose, Chaudhuri and Hocquengham (BCH) ECC algorithm.
When a BCH 8 ECC algorithm encodes the data in the NAND flash memory, the parity code generated in the encoding
process may occupy 13 bytes of the spare area in each page. When a BCH 15 ECC algorithm encodes the data in the
NAND flash memory, the parity code generated in the encoding process may occupy 25 bytes of the spare in each page.
When a BCH 8 algorithm decodes the data in the NAND flash memory, the data can be decoded correctly if the error bit
happened in one sector (512 Bytes) is 8. When a BCH 15 algorithm decodes the data in the NAND flash memory, the data
can be decoded correctly if the error bit happened in one sector is 15.
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