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Intel® Atom™ processor CE4100 Platform Design Guide May 2010 Revision 1.5 Intel Confidential Reference Number: 420826

10 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Revision History Date Revision Reference # Description

100 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Figure 8-9. GBE Interface Clock Signal Design Example Int

Ref# 420826 Intel® Atom™ processor CE4100 101 Platform Design Guide Intel Confidential Figure 8-12. GBE_TXCTL Figure 8-13. GBE_REFCLK Tab

102 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Figure 8-14. GBE_RXDATA<0~3> and GBE_RXCLK Table

Ref# 420826 Intel® Atom™ processor CE4100 103 Platform Design Guide Intel Confidential 8.4 Expansion Bus Interface Guidelines The expansion

104 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.4.1 Expansion Bus Chip Select The Expansion Bus includ

Ref# 420826 Intel® Atom™ processor CE4100 105 Platform Design Guide Intel Confidential 8.4.2 Expansion Bus Address, EXP_ALE and EXP_IO_WRB

106 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.4.3 Data Bus A EXP_DATA_A and EXP_DATA_B, EXP_DATA_A

Ref# 420826 Intel® Atom™ processor CE4100 107 Platform Design Guide Intel Confidential 8.4.4 Data Bus B and Control Signals Data bus B has

108 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.5 NAND Flash The NAND Flash Controller used in the Int

Ref# 420826 Intel® Atom™ processor CE4100 109 Platform Design Guide Intel Confidential 8.5.3 NAND_IO Topology Traces Layer Min Length

Ref# 420826 Intel® Atom™ processor CE4100 11 Platform Design Guide Intel Confidential 11 IInnttrroodduuccttiioonn This Intel® Atom™ process

110 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.5.4 NAND_WE_N, NAND_RE_N, NAND_CLE and NAND_ALE Topolo

Ref# 420826 Intel® Atom™ processor CE4100 111 Platform Design Guide Intel Confidential 8.5.5 NAND_CE_N Topology Traces Layer Min Length

112 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.5.6 NAND_RY_BY_N Signal Recommendation SodavilleNAND1

Ref# 420826 Intel® Atom™ processor CE4100 113 Platform Design Guide Intel Confidential 8.5.7 NAND_CLK_X_OUT/IN Topology Traces Layer Pa

114 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.6 I2C* Interface The I2C Bus Interface Unit allows th

Ref# 420826 Intel® Atom™ processor CE4100 115 Platform Design Guide Intel Confidential 8.7 UART Interface There are two high-speed UART int

116 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.7.1 UART0_RXD Signal Recommendation Figure 8-22. UART0

Ref# 420826 Intel® Atom™ processor CE4100 117 Platform Design Guide Intel Confidential 8.7.2 UART0_DSRB Signal Recommendation Figure 8-23. U

118 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.8 GPIO Interface The General Purpose I/O interface pr

Ref# 420826 Intel® Atom™ processor CE4100 119 Platform Design Guide Intel Confidential Figure 8-24. GPIO Interface Topology Table 8-15. GPI

12 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 1.1 Related Documents Table 1-1 provides a list of relat

120 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.9 SPI Serial Interface The SPI serial interface on th

Ref# 420826 Intel® Atom™ processor CE4100 121 Platform Design Guide Intel Confidential 8.9.2 SPI_MISO Routing Recommendation Figure 8-25. SP

122 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.9.3 SPI_MOSI and SPI_SCK Routing Recommendation Figure

Ref# 420826 Intel® Atom™ processor CE4100 123 Platform Design Guide Intel Confidential 8.9.4 SPI_SS Signal Routing Recommendation Figure 8-2

124 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.10 Smart Card Interface The Intel® Atom™ processor CE

Ref# 420826 Intel® Atom™ processor CE4100 125 Platform Design Guide Intel Confidential 8.10.1 Smart Card Signal Routing Recommendation Figur

126 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 99 HHiigghh DDeeffiinniittiioonn VViiddeeoo CCaappttu

Ref# 420826 Intel® Atom™ processor CE4100 127 Platform Design Guide Intel Confidential Table 9-1. Video Input Mode Description

128 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 9.2 HDVCAP Routing Topology 9.2.1 HDVCAP Design Topolog

Ref# 420826 Intel® Atom™ processor CE4100 129 Platform Design Guide Intel Confidential 9.2.2 HDVCAP Design Topology 2 Figure 9-3. HDVCAP Sig

Ref# 420826 Intel® Atom™ processor CE4100 13 Platform Design Guide Intel Confidential Intel® Atom™ processor CE4100 Documents Note: The follo

130 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 1100 PPllaattffoorrmm CClloocckk DDeessiiggnn GGuuiid

Ref# 420826 Intel® Atom™ processor CE4100 131 Platform Design Guide Intel Confidential The diagram below shows the clocking scheme example on

132 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 10.1 Reference Clock Routing Guidelines 10.1.1 CK505

Ref# 420826 Intel® Atom™ processor CE4100 133 Platform Design Guide Intel Confidential Table 10-1. CK505 Clock Routing Guidelines Parameters

134 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Figure 10-4. IDT6V49061 HDMI Reference Clock Topology No

Ref# 420826 Intel® Atom™ processor CE4100 135 Platform Design Guide Intel Confidential 10.1.2.2 Audio and VDC Clock Input Design Example The

136 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 10.2 Audio Reference Clock Output Routing Recommendation

Ref# 420826 Intel® Atom™ processor CE4100 137 Platform Design Guide Intel Confidential 10.3 VCXO Mode Design Guidelines The Voltage-controll

138 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential How to test this VCXO tuning on board: 1. The VCXO shoul

14 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential JEDEC DDR3 Specifications http://www.jedec.org Low Pin C

Ref# 420826 Intel® Atom™ processor CE4100 15 Platform Design Guide Intel Confidential 1.2 Acronyms and Terminology Table 1-2. Acronyms and

16 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Acronym Definition DVB Digital Video Broadcasting — a

Ref# 420826 Intel® Atom™ processor CE4100 17 Platform Design Guide Intel Confidential Acronym Definition NIM Network Interface Module — i

18 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential This page intentionally left blank

Ref# 420826 Intel® Atom™ processor CE4100 19 Platform Design Guide Intel Confidential 22 PPllaattffoorrmm OOvveerrvviieeww The Intel® At

2 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Legal Statements INFORMATION IN THIS DOCUMENT IS PROVIDED I

20 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Figure 2-1. Platform Overview

Ref# 420826 Intel® Atom™ processor CE4100 21 Platform Design Guide Intel Confidential 33 PPllaattffoorrmm SSttaacckk--uupp aanndd GGeenne

22 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Note The guidelines recommended in this document are ba

Ref# 420826 Intel® Atom™ processor CE4100 23 Platform Design Guide Intel Confidential Figure 3-1. Recommended 6-layer PCB Stack-up Dimensions

24 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Figure 3-2. Recommended 4-layer PCB Stack-up Dimensions

Ref# 420826 Intel® Atom™ processor CE4100 25 Platform Design Guide Intel Confidential 3.1.1 1080 Prepreg To achieve the stack-up described i

26 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 3.1.3 Multiple Impedance Target Considerations This plat

Ref# 420826 Intel® Atom™ processor CE4100 27 Platform Design Guide Intel Confidential 44 PPllaattffoorrmm PPoowweerr DDiissttrriibbuuttiio

28 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 4.2 General Power Rail Design Guidelines • Place edge de

Ref# 420826 Intel® Atom™ processor CE4100 29 Platform Design Guide Intel Confidential 4.3 Power Decoupling Table 4-1. Decoupling Example No

Ref# 420826 Intel® Atom™ processor CE4100 3 Platform Design Guide Intel Confidential Contents 1 Introduction...

30 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Voltage/ Interface Voltage Isolation Value Qty Size Typ

Ref# 420826 Intel® Atom™ processor CE4100 31 Platform Design Guide Intel Confidential 4.4 Power Sequence From a power management point of v

32 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 4.4.1 Power-On Sequence Example On the development platf

Ref# 420826 Intel® Atom™ processor CE4100 33 Platform Design Guide Intel Confidential 4.5 Reset Sequence RESET_INB and SYS_PWR_GOOD signal

34 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 4.5.1 Reset Sequence Examples The section lists the warm

Ref# 420826 Intel® Atom™ processor CE4100 35 Platform Design Guide Intel Confidential 4.5.1.2 Cold Reset Sequence PS_ON_PIC (PIC)3.3V stand

36 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 4.5.1.3 Catastrophic Shutdown An internal shutdown would

Ref# 420826 Intel® Atom™ processor CE4100 37 Platform Design Guide Intel Confidential 4.6 Straps The following table lists all of the straps

38 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Strap Name Pin Name Description DDR_SPEED EXP_ADDR[8:6]

Ref# 420826 Intel® Atom™ processor CE4100 39 Platform Design Guide Intel Confidential 4.7 Expansion Bus Strapping Design Topology The Expans

4 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 6.1.2 Video Calibration Circuit ...

40 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 4.7.2 Design Example Two This design topology is used on

Ref# 420826 Intel® Atom™ processor CE4100 41 Platform Design Guide Intel Confidential 4.8 Debug Port Guidelines Please refer to the latest

42 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 55 SSyysstteemm MMeemmoorryy DDeessiiggnn GGuuiiddeell

Ref# 420826 Intel® Atom™ processor CE4100 43 Platform Design Guide Intel Confidential 5.2 DDR2/DDR3 Pin Descriptions Table 5-3 provides a s

44 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 5.4 Package Length Compensation Package length compensat

Ref# 420826 Intel® Atom™ processor CE4100 45 Platform Design Guide Intel Confidential Channel A Channel B Signal Name Package Length (mils)

46 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 5.5 DDR3 Design Topologies and Routing Guidelines 5.5.1

Ref# 420826 Intel® Atom™ processor CE4100 47 Platform Design Guide Intel Confidential Table 5-6. DDR3 Memory Clock Topology Table Traces Desc

48 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential The VREF, which is 1/2 of VCC1P5_DDR (VCC1P5_DDR for DDR2)

Ref# 420826 Intel® Atom™ processor CE4100 49 Platform Design Guide Intel Confidential 5.5.1.3 Data and Data Strobe Signals – DQ/DM/DQS Table

Ref# 420826 Intel® Atom™ processor CE4100 5 Platform Design Guide Intel Confidential 9 High Definition Video Capture (HDVCAP) ...

50 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Table 5-10. DDR3 DQ/DM/DQS Topology Table Traces Descrip

Ref# 420826 Intel® Atom™ processor CE4100 51 Platform Design Guide Intel Confidential Table 5-12. DDR3 Memory Clock Topology Table Traces D

52 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 5.5.2.2 Address, Command and Control Table 5-13. Address,

Ref# 420826 Intel® Atom™ processor CE4100 53 Platform Design Guide Intel Confidential Table 5-14. DDR3 Address, Command, and Control Topolog

54 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 5.5.2.3 Data and Data Strobe Signals – DQ/DM/DQS Table 5-

Ref# 420826 Intel® Atom™ processor CE4100 55 Platform Design Guide Intel Confidential 5.6 DDR2 Design Topology and Routing Guidelines 5.6.1

56 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Table 5-18. DDR2 Memory Clock Topology Table Traces Descri

Ref# 420826 Intel® Atom™ processor CE4100 57 Platform Design Guide Intel Confidential Figure 5-8. DDR2 Address, Command and Control Topology

58 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 5.6.1.3 Data and Data Strobe Signals – DQ/DM/DQS Table 5-

Ref# 420826 Intel® Atom™ processor CE4100 59 Platform Design Guide Intel Confidential Table 5-22. DDR2 DQ/DM/DQS Topology Table Traces Des

6 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential List of Tables Table 1-1. Related Documents ...

60 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 5.6.2 DDR2 Guidelines for x8 Devices 5.6.2.1 Clock Signa

Ref# 420826 Intel® Atom™ processor CE4100 61 Platform Design Guide Intel Confidential Table 5-24. DDR2 Memory Clock Topology Table Traces D

62 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 5.6.2.2 Address, Command and Control Table 5-25. Address,

Ref# 420826 Intel® Atom™ processor CE4100 63 Platform Design Guide Intel Confidential Table 5-26. DDR2 Address, Command, and Control Topolog

64 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 5.6.2.3 Data and Data Strobe Signals – DQ/DM/DQS Table 5-

Ref# 420826 Intel® Atom™ processor CE4100 65 Platform Design Guide Intel Confidential 5.7 VREF Circuit Figure 5-13 shows the DDR2/3 VREF ci

66 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 5.8 Miscellaneous Signals Design Guidelines The DDR2/3 i

Ref# 420826 Intel® Atom™ processor CE4100 67 Platform Design Guide Intel Confidential 66 VViiddeeoo OOuuttppuutt IInntteerrffaacceess Thi

68 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential General layout design guide • Dedicatedly isolated analog

Ref# 420826 Intel® Atom™ processor CE4100 69 Platform Design Guide Intel Confidential Figure 6-1. VDAC application Model 1: VDAC with Integra

Ref# 420826 Intel® Atom™ processor CE4100 7 Platform Design Guide Intel Confidential Table 8-4. USB Channel Routing Guidelines...

70 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Figure 6-2. VDAC application Model 2: VDAC with Discrete F

Ref# 420826 Intel® Atom™ processor CE4100 71 Platform Design Guide Intel Confidential The passive configuration has not been validated, but i

72 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Figure 6-4. VBG_EXTR_VDAC Connection Figure 6-4 provides

Ref# 420826 Intel® Atom™ processor CE4100 73 Platform Design Guide Intel Confidential 6.1.2 Video Calibration Circuit The Intel® Atom™ proce

74 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 6.2 HDMI Transmitter Interface The Intel® Atom™ processor

Ref# 420826 Intel® Atom™ processor CE4100 75 Platform Design Guide Intel Confidential 6.2.1 Detailed HDMI Routing Example Figure 6-9. 4-pai

76 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Table 6-2. HDMI Transmitter Routing Guidelines for the 10

Ref# 420826 Intel® Atom™ processor CE4100 77 Platform Design Guide Intel Confidential 6.2.2 HDMI ESD Protector Routing Suggestions Due to th

78 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Figure 6-10. Using an IP4777CZ38 ESD Device Example – 6+ L

Ref# 420826 Intel® Atom™ processor CE4100 79 Platform Design Guide Intel Confidential Figure 6-11. Using an IP4777CZ38 ESD Device Example – 4

8 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential List of Figures Figure 2-1. Platform Overview ...

80 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Notes: • There is a GND trench on layer 2 as indicated in

Ref# 420826 Intel® Atom™ processor CE4100 81 Platform Design Guide Intel Confidential Figure 6-12. Using a CM2030 or TPD12S521 ESD Device Exa

82 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Figure 6-13. Using a CM2030 or TPD12S521 ESD Device Exampl

Ref# 420826 Intel® Atom™ processor CE4100 83 Platform Design Guide Intel Confidential Notes: • There is a GND trench on layer 2 as indicated

84 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 6.3.1 TS Interface Routing Topology Example The topology

Ref# 420826 Intel® Atom™ processor CE4100 85 Platform Design Guide Intel Confidential 77 AAuuddiioo IInntteerrffaacceess 7.1 Overview Th

86 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 7.3 I2S Audio Output Interface This interface includes I

Ref# 420826 Intel® Atom™ processor CE4100 87 Platform Design Guide Intel Confidential 7.4 S/PDIF Audio Interface This S/PDIF interface suppo

88 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 88 OOtthheerr IInntteerrffaacceess 8.1 Serial ATA (SAT

Ref# 420826 Intel® Atom™ processor CE4100 89 Platform Design Guide Intel Confidential 8.1.1 SATA Routing Guidelines The SATA interface has

Ref# 420826 Intel® Atom™ processor CE4100 9 Platform Design Guide Intel Confidential Figure 8-7. USBRBIAS/USBRBIASN Connection ...

90 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.1.1.1 Serial ATA Trace Separation Use the following s

Ref# 420826 Intel® Atom™ processor CE4100 91 Platform Design Guide Intel Confidential 8.1.1.2 Serial ATA Trace Length Guidelines Table 8-1.

92 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.1.1.3 Serial ATA AC Coupling Requirements The Intel®

Ref# 420826 Intel® Atom™ processor CE4100 93 Platform Design Guide Intel Confidential 8.1.2 Terminating Unused SATA Signals If the SATA po

94 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.2 USB 2.0 The Universal Serial Bus (USB) is a cable bu

Ref# 420826 Intel® Atom™ processor CE4100 95 Platform Design Guide Intel Confidential 8.2.1.1 USB 2.0 Trace Separation Use the following sep

96 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential Table 8-4. USB Channel Routing Guidelines Parameter Rout

Ref# 420826 Intel® Atom™ processor CE4100 97 Platform Design Guide Intel Confidential 8.2.1.2 USBRBIAS/USBRBIASN Connection Intel recommend

98 Intel® Atom™ processor CE4100 Ref# 420826 Platform Design Guide Intel Confidential 8.2.1.3 USB Power Sequence With more and more USB devices

Ref# 420826 Intel® Atom™ processor CE4100 99 Platform Design Guide Intel Confidential 8.3 Gigabit Ethernet The Gigabit Ethernet Media Acces