Samsung LNB50 Bedienungsanleitung PDF herunterladen (Seite 103)

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U PCM

The T7256 U transceiver generates a 2.048-MHz PCLK that can be directly

connected to the DSLAC device’s PCLK and MCLK inputs.

NOTE: HDLC channel C and GCI are supported only on the Am186CC

communications controller.

MCLK is the master clock used to drive the DSLAC device’s internal DSP. MCLK

must be 2.048 MHz or 4.096 MHz and can be asynchronous to the DSLAC device’s

PCLK input. The MCLK input is derived from whichever ISDN transceiver is being

used as the upstream ISDN device. If the U interface is selected using the T7256

as the clock master, MCLK is derived directly from the 2.048-MHz CLKA output

from the T7256A. If the S/T interface is selected as the clock master, PCLK is

derived from the Am79C32A DSC circuit MCLK output (MCLK_C32) or from

the output and PLD U20, which synchronizes the DSLAC MCLK input to its PCLK

input. Table 3-5 shows MCLK jumper configuration.

Table 3-5. Am79C031 DSLAC™ Device PCLK/FS/MCLK Configuration

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1. U20 is used to modify the clocks to properly synchronize to the DSLAC device’s PCM timing.

2. Requires PAL at U20 to use PLD code module_20_u20_gci_00 for IOM-2 mode, and module_20_u20_PCM_00

for SBP mode.

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3. PCLK and FS for the DSLAC device are generated by the Am186CC communications controller.

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Samsung LNB50 Bedienungsanleitung Seite 103